Semiconductor devices such as logic and memory devices are typically fabricated by a sequence of processing steps applied to a specimen. The various features and multiple structural levels of the semiconductor devices are formed by these processing steps. For example, lithography among others is one semiconductor fabrication process that involves generating a pattern on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated on a single semiconductor wafer and then separated into individual semiconductor devices.
Metrology processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield. A number of metrology based techniques including scatterometry and reflectometry implementations and associated analysis algorithms are commonly used to characterize critical dimensions, film thicknesses, composition and other parameters of nanoscale structures.
Most advanced logic and memory devices fabricated at semiconductor device fabrication nodes below 20 nanometers are constructed using multiple patterning processes. Exemplary multiple patterning processes include self-aligned double patterning (SADP), self-aligned triple patterning (SATP), and self-aligned quadruple patterning (SAQP) techniques.
In one example, a SAQP fin formation process achieves a target pitch that is one-quarter of the pitch obtainable with conventional single pattern lithography. In one example, at least fourteen steps are required to generate the fin structures. These steps include lithography, etch, and strip steps that must be precisely controlled to realize the fin structures with the desired pitch and profile. The final pitch values and fin profile (e.g. CD, SWA) achieved by the SAQP fin formation process are impacted by structural parameter values from previous steps (e.g., resist profile parameters, spacer film thicknesses, and others).
Currently, measurements of overlay are predominantly performed using optical methods, based on either optical imaging or non-imaging diffraction (scatterometry). However, these approaches have not reliably overcome fundamental challenges associated with measurement of many advanced targets (e.g., complex 3D structures, structures smaller than 10 nm, structures employing opaque materials) and measurement applications (e.g., line edge roughness and line width roughness measurements).
As devices (e.g., logic and memory devices) move toward smaller nanometer-scale dimensions, characterization becomes more difficult. Devices incorporating complex three-dimensional geometry and materials with diverse physical properties contribute to characterization difficulty. For example, modern memory structures are often high-aspect ratio, three-dimensional structures that make it difficult for optical radiation to penetrate to the bottom layers. Optical metrology tools utilizing infrared to visible light can penetrate many layers of translucent materials, but longer wavelengths that provide good depth of penetration do not provide sufficient sensitivity to small anomalies. In addition, the increasing number of parameters required to characterize complex structures (e.g., FinFETs), leads to increasing parameter correlation. As a result, the parameters characterizing the target often cannot be reliably decoupled with available measurements. For some structural parameters, such as edge placement error (EPE), there is currently no high throughput (e.g., optical) measurement solution.
In another example, opaque, high-k materials are increasingly employed in modern semiconductor structures. Optical radiation is often unable to penetrate layers constructed of these materials. As a result, measurements with thin-film scatterometry tools such as ellipsometers or reflectometers are becoming increasingly challenging.
In some examples, optical overlay metrology is also employed, but optical overlay measurements require specialized metrology targets to characterize structures fabricated by multiple patterning techniques. In existing methods, overlay error is typically evaluated based on measurements of specialized target structures formed at various locations on the wafer by a lithography tool. The target structures may take many forms, such as a box in box structure. In this form, a box is created on one layer of the wafer and a second, smaller box is created on another layer. The localized overlay error is measured by comparing the alignment between the centers of the two boxes. Such measurements are taken at locations on the wafer where target structures are available.
Unfortunately, these specialized target structures often do not conform to the design rules of the particular semiconductor manufacturing process being employed to generate the electronic device. This leads to errors in estimation of overlay errors associated with actual device structures that are manufactured in accordance with the applicable design rules.
In one example, image-based optical overlay metrology is severely limited by the resolution of imaging at optical wavelengths. Thus, only targets with features much larger than the design rule can be measured. Image-based optical overlay metrology often requires the pattern to be resolved with an optical microscope that requires thick lines with critical dimensions far exceeding design rule critical dimensions.
In another example, scatterometry-based optical overlay metrology based on 0th order diffraction has very low sensitivity to small overlay errors as the sensitivity decreases with the pitch of the periodic targets. This drives the pitch to much larger dimensions than the design rule of the device. Moreover, the accuracy of this measurement approach degrades dramatically in the presence of any asymmetry in any of the layers where overlay is measured. In addition, this approach cannot differentiate between positive and negative overlay errors in a single measurement.
In another example, scatterometry-based optical overlay metrology based on diffraction orders higher than zero also require relatively large pitch targets to generate sufficient signal at nonzero propagating diffraction orders. In some examples, pitch values in the range 500-800 nm may be used. Meanwhile, actual device pitches for logic or memory applications (design rule dimensions) may be much smaller, e.g., in the range 100-400 nm, or even below 100 nm. In addition, the accuracy of this approach degrades dramatically in the presence of any asymmetry in any of the layers where overlay is measured.
Atomic force microscopes (AFM) and scanning-tunneling microscopes (STM) are able to achieve atomic resolution, but they can only probe the surface of the specimen. In addition, AFM and STM microscopes require long scanning times.
Scanning electron microscopes (SEM) achieve intermediate resolution levels, but are unable to penetrate structures to sufficient depth without destroying the sample. Thus, high-aspect ratio holes are not characterized well. In addition, the required charging of the specimen has an adverse effect on imaging performance.
Transmission electron microscopes (TEM) achieve high resolution levels and are able to probe arbitrary depths, but TEM requires destructive sectioning of the specimen.
In another example, an x-ray overlay measurement method is based on identifying the diffracted x-ray energy redistribution between the diffraction orders (“lobes”) at a fixed (normal) incidence. This approach is described in U.S. Pat. No. 7,481,579 to Yokhim et al., and assigned to Jordan Valley Applied Radiation, Ltd. This quantity has a relatively low sensitivity to overlay and is strongly correlated to CD geometrical parameters because it does not consider the intensity distribution within each diffraction order. Thus, either an external metrology system or a computationally expensive simulation is required to calibrate out the effect of CD. Either of these approaches is limited in accuracy and precision due to the high correlation between CD parameters (e.g., asymmetry) and overlay.
In another example, an x-ray overlay measurement method is based on a modulation of the measured intensity signal as the wafer is rotated about an axis that lies in the plane of wafer surface. Further details are described in U.S. Patent Publication No. 2015/0117610 A1 by Veldman et al., the contents of which are incorporated herein by reference in their entirety. In this example, the measured periodicity is projected into the dimension normal to the wafer surface, but not into a direction parallel to the wafer surface and perpendicular to the periodic dimension.
In summary, semiconductor device yield at device fabrication nodes below 20 nanometers for logic devices and advanced DRAM, and vertical or planar NAND devices is a complex function of many parameters, including film thicknesses, profile parameters of patterned lines, overlay errors, and edge placement errors (EPE). Of these, EPE has the most demanding process window and requires metrology and control of CD and overlay. Currently there is no high-throughput, optical metrology solution for EPE measurements and many on-device overlay measurement applications. In addition, the absence of adequate metrology makes it challenging to define control schemes to improve device yield.
Future metrology applications present challenges for metrology due to increasingly small resolution requirements, multi-parameter correlation, increasingly complex geometric structures, and increasing use of opaque materials. Thus, methods and systems for improved overlay and shape measurements are desired.